The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2020

Filed:

Sep. 05, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventors:

Kunifumi Suzuki, Yokkaichi Mie, JP;

Kazuhiko Yamamoto, Yokkaichi Mie, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/1157 (2017.01); G11C 7/06 (2006.01); G11C 16/24 (2006.01); G11C 16/14 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 7/06 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/14 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); H01L 27/1157 (2013.01);
Abstract

According to one embodiment, a nonvolatile semiconductor memory device includes a first interconnect layer provided above a semiconductor substrate; a plurality of second interconnect layers provided above the first interconnect layer; a semiconductor layer electrically coupled to the first interconnect layer; a first insulating layer provided between the semiconductor layer and the plurality of second interconnect layers; and a plurality of first oxide layers in which one side of the first oxide layers is in contact with the plurality of second interconnect layers while the other side of the first oxide layers is in contact with the first insulating layer, and a voltage is applied to the plurality of second interconnect layers to vary a resistance value.


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