The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 26, 2020
Filed:
Feb. 16, 2016
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Stephen M. Trimberger, Incline Village, NV (US);
Mohsen H. Mardi, Saratoga, CA (US);
David M. Mahoney, Gilroy, CA (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 25/18 (2006.01); H01L 25/065 (2006.01); H01L 23/538 (2006.01); H01L 25/16 (2006.01); H01L 23/13 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 23/5385 (2013.01); H01L 24/17 (2013.01); H01L 25/0652 (2013.01); H01L 25/0655 (2013.01); H01L 25/0657 (2013.01); H01L 25/16 (2013.01); H01L 23/13 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16148 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/81193 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/06572 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15153 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/19107 (2013.01);
Abstract
A chip package assembly is provided that includes a substrate, at least one integrated circuit (IC) die and a power management integrated circuit (PMIC). In one example, the IC die of the chip package assembly is disposed on a first surface of the substrate. The PMIC die has a first surface having outputs electrically coupled to the second surface of the IC die. The PMIC die also has a second surface facing away from the first surface. The second surface of the PMIC die has inputs that are electrically coupled to the first surface of the substrate.