The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2020

Filed:

Sep. 27, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Eun-seok Song, Hwaseong-si, KR;

Chan-kyung Kim, Hwaseong-si, KR;

Tae-joo Hwang, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 25/10 (2006.01); H01L 23/498 (2006.01); G11C 5/06 (2006.01); G11C 5/04 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); G11C 5/04 (2013.01); G11C 5/06 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 24/04 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 24/73 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/13101 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13116 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73215 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/92125 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15174 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01);
Abstract

A semiconductor package includes: a memory sub-package including a first connecting layer and a plurality of memory chips disposed on the first connecting layer; a logic sub-package including a second connecting layer, a controller chip disposed on the second connecting layer, and a buffer chip connected to the controller chip and the plurality of memory chips; and a plurality of inter-package connecting members each of which connects the memory sub-package and the logic sub-package, wherein the buffer chip is connected to the plurality of memory chips via a plurality of first data transfer lines each having a first data transfer rate, the buffer chip is connected to the controller chip via a plurality of second data transfer lines each having a second data transfer rate, and the first data transfer rate is less than the second data transfer rate.


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