The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2020

Filed:

Jun. 27, 2018
Applicant:

Semikron Elektronik Gmbh & Co. KG, Nuremberg, DE;

Inventor:

Ulrich Sagebaum, Feucht, DE;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/14 (2006.01); H01L 23/15 (2006.01);
U.S. Cl.
CPC ...
H01L 24/29 (2013.01); H01L 23/145 (2013.01); H01L 23/15 (2013.01); H01L 24/27 (2013.01); H01L 24/32 (2013.01); H01L 24/50 (2013.01); H01L 24/83 (2013.01); H01L 24/05 (2013.01); H01L 24/33 (2013.01); H01L 24/75 (2013.01); H01L 24/79 (2013.01); H01L 24/86 (2013.01); H01L 2224/04026 (2013.01); H01L 2224/2732 (2013.01); H01L 2224/2783 (2013.01); H01L 2224/2784 (2013.01); H01L 2224/291 (2013.01); H01L 2224/29017 (2013.01); H01L 2224/29019 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/29294 (2013.01); H01L 2224/29339 (2013.01); H01L 2224/32227 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/50 (2013.01); H01L 2224/73269 (2013.01); H01L 2224/75303 (2013.01); H01L 2224/79303 (2013.01); H01L 2224/8384 (2013.01); H01L 2224/83345 (2013.01); H01L 2224/83447 (2013.01); H01L 2224/83862 (2013.01); H01L 2224/8684 (2013.01); H01L 2924/10158 (2013.01);
Abstract

A power electronics method and assembly produced by the method. The assembly has a substrate, having a power semiconductor element, and an adhesion layer disposed therebetween, wherein the substrate has a first surface that faces a power semiconductor element, a power semiconductor element has a third surface that faces the substrate, the adhesion layer has a second surface which, preferably across the full area, contacts the third surface and has a first consistent surface contour having a first roughness, and wherein a fourth surface of the power semiconductor element that is opposite the third surface has a second surface contour having a second roughness, said second surface contour following the first surface contour.


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