The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2020

Filed:

Jul. 16, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sihong Kim, Hwaseong-si, KR;

Young-Hoon Son, Hwaseong-si, KR;

Taeyoung Oh, Seoul, KR;

Kyung-Soo Ha, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); G11C 5/06 (2006.01); G11C 8/10 (2006.01); G11C 5/04 (2006.01); G11C 5/02 (2006.01);
U.S. Cl.
CPC ...
H01L 24/06 (2013.01); G11C 5/025 (2013.01); G11C 5/04 (2013.01); G11C 5/06 (2013.01); G11C 5/063 (2013.01); G11C 8/10 (2013.01); H01L 24/02 (2013.01); G11C 2207/105 (2013.01); H01L 2224/02375 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/06154 (2013.01); H01L 2224/06158 (2013.01); H01L 2924/1434 (2013.01);
Abstract

A semiconductor memory includes a plurality of first pads arranged in a first direction, a plurality of second pads arranged parallel to the plurality of first pads and in the first direction, a plurality of third pads arranged in a second direction perpendicular to the first direction, and a plurality of fourth pads arranged in the second direction. The semiconductor memory further includes first interconnection wires extending from the plurality of first pads in the second direction, the first interconnection wires being connected to the plurality of third pads, and second interconnection wires extending from the plurality of second pads in an opposite direction to the second direction, the second interconnection wires being connected to the plurality of fourth pads.


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