The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2020

Filed:

Mar. 08, 2017
Applicant:

Marvell International Ltd., Hamilton, BM;

Inventors:

Cao-Thong Tu, Preverenges, CH;

Konstantinos Manetakis, Lausanne, CH;

Xiang Gao, Fremont, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01F 17/00 (2006.01); H01F 27/28 (2006.01); H01F 27/40 (2006.01); H01F 41/04 (2006.01);
U.S. Cl.
CPC ...
H01F 27/2804 (2013.01); H01F 27/2885 (2013.01); H01F 27/40 (2013.01); H01F 41/041 (2013.01);
Abstract

Embodiments described herein provide circuitry employing an inductor having enhanced circuit area usage. The circuitry includes an inductor having a first loop and a second loop adjoining the first loop to form a figure-eight configuration. The circuitry further includes a circuit component disposed at least partially inside an area defined by at least one of the first loop and the second loop. The inductor has an intersection portion between the first loop and the second loop. An input node is located proximate to the intersection portion, the input node having a first extension disposed inside the first loop. An output node is located proximate to the intersection portion. The output node has a second extension disposed inside the second loop. At least a first capacitor is coupled to the input node and the second extension, and at least a second capacitor coupled to the output node and the first extension.


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