The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2020

Filed:

Aug. 29, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventor:

Yohei Yasuda, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 19/28 (2006.01); G11C 7/06 (2006.01); H03K 19/0944 (2006.01); H03K 19/0185 (2006.01); G11C 5/06 (2006.01); H03K 3/3562 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1051 (2013.01); G11C 5/06 (2013.01); G11C 7/065 (2013.01); G11C 7/222 (2013.01); G11C 19/28 (2013.01); H03K 3/35625 (2013.01); H03K 19/01855 (2013.01); H03K 19/0944 (2013.01);
Abstract

A semiconductor device having a first inverter electrically connected to a first node. A second inverter is electrically connected to a second node. A third clocked inverter is electrically connected to an output node of the first inverter. A fourth clocked inverter is electrically connected to an output node of the second inverter. A third inverter is electrically connected to an output node of a first clocked inverter and an output node of a second clocked inverter. A fourth inverter is electrically connected to an output node of the third clocked inverter and an output node of the fourth clocked inverter. A comparison circuit is electrically connected to an output node of the third inverter and an output node of the fourth inverter.


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