Semiconductor memory devices, memory systems and refresh methods of the same

Abstract

A memory controller transmits one or more command pairs of a self-refresh entry command and a subsequent self-refresh exit command to a semiconductor memory device during a refresh period. The semiconductor memory device includes a memory cell array including a plurality of memory cell rows each including a plurality of dynamic memory cells, and a refresh control circuit. The refresh control circuit performs a refresh operation on all of the memory cell rows during the refresh period in a self-refresh mode, the self-refresh mode of the refresh period being configured in response to each self-refresh entry command of the one or more command pairs, for each of the one or more command pairs, the memory controller sequentially transmits during the refresh period at least one self-refresh entry command and at least one self-refresh exit command to the semiconductor memory device separated by one or more time gaps.