The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2020

Filed:

Oct. 03, 2018
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Koichi Takeda, Tokyo, JP;

Takashi Iwase, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); H03K 19/0185 (2006.01); G11C 7/10 (2006.01); G11C 8/08 (2006.01); G11C 8/14 (2006.01); G11C 8/18 (2006.01); H03K 5/1534 (2006.01); G11C 8/10 (2006.01);
U.S. Cl.
CPC ...
G11C 5/14 (2013.01); G11C 7/1093 (2013.01); G11C 8/08 (2013.01); G11C 8/14 (2013.01); G11C 8/18 (2013.01); H03K 19/0185 (2013.01); H03K 19/018521 (2013.01); G11C 8/10 (2013.01); H03K 5/1534 (2013.01);
Abstract

According to an embodiment, a word line driver includes: a first inverter that is driven by a first power supply voltage and inverts and outputs a decode signal; a second inverter that is driven by a second power supply voltage and inverts and outputs the decode signal; a first PMOS transistor that is controlled to be turned on or off on the basis of an output signal of the second inverter; a first NMOS transistor that is controlled to be turned on or off on the basis of an output signal of the first inverter; and a second PMOS transistor that is provided between a power supply voltage terminal to which the second power supply voltage is supplied and the gate of the first PMOS transistor and is temporarily turned on in synchronization with falling of the decode signal.


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