The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2020

Filed:

Jan. 17, 2019
Applicants:

Memray Corporation, Seoul, KR;

Yonsei University, University—industry Foundation (Uif), Seoul, KR;

Inventors:

Myoungsoo Jung, Incheon, KR;

Gyuyoung Park, Incheon, KR;

Miryeong Kwon, Incheon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G11C 14/00 (2006.01); G11C 13/00 (2006.01); G06F 13/16 (2006.01); G06F 12/0804 (2016.01); G06F 12/0895 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0804 (2013.01); G06F 12/0895 (2013.01); G11C 14/0045 (2013.01); G06F 13/1694 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/608 (2013.01); G11C 13/0069 (2013.01);
Abstract

A memory controlling device configured to connect to a first memory module including a resistance switching memory cell array which is partitioned into a plurality of partitions and a second memory module used for a cache is provided. A cache controller splits an address of a read request into at least a first cache index and a first tag, and determines whether the read request is a cache hit or a cache miss by referring to a lookup logic based on the first cache index and the first tag. The cache controller instructs the memory controller to read target data of the read request from the first memory module when the read request targets to the second partition in a case where the read request is the cache miss and a write to the first partition is in progress.


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