The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2020

Filed:

Oct. 01, 2018
Applicant:

Sony Corporation, Tokyo, JP;

Inventors:

Thomas Ayers, Morgan Hill, CA (US);

Jinsuk Kang, Palo Alto, CA (US);

Brian Carey, Sunnyvale, CA (US);

Noam Eshel, Pardesia, IL;

Frederick Brady, Webster, NY (US);

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/378 (2011.01); H04N 5/225 (2006.01); H04N 5/232 (2006.01); H04N 5/357 (2011.01); H04N 5/363 (2011.01); H04N 5/369 (2011.01); H04N 5/374 (2011.01); H01L 27/146 (2006.01); H04N 5/3745 (2011.01);
U.S. Cl.
CPC ...
H04N 5/378 (2013.01); H01L 27/14612 (2013.01); H04N 5/2251 (2013.01); H04N 5/23245 (2013.01); H04N 5/3575 (2013.01); H04N 5/363 (2013.01); H04N 5/369 (2013.01); H04N 5/3742 (2013.01); H04N 5/37455 (2013.01);
Abstract

An image sensor including a pixel circuit and an active reset circuit. The pixel circuit includes a light sensing element, a storage node selectively connected to the light sensing element, an output transistor configured to, during a readout operation, output a signal that is based on a potential of the charge storage node to an output line, and a selection transistor that controls the readout operation. The active reset circuit includes a first current path and a second current path, the first current path extending from a power supply node to the output line via the selection transistor and the output transistor, and the second current path extending from the power supply node to the output line via a first transistor and a second transistor. The active reset circuit is configured to, when the selection transistor and the first transistor are both ON, set a potential of the charge storage node based on a potential of a gate of the second transistor.


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