The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2020
Filed:
Jun. 04, 2019
Applicant:
Sony Corporation, Tokyo, JP;
Inventors:
Takanori Saeki, Tokyo, JP;
Tomohiro Takahashi, Tokyo, JP;
Yuiti Takeda, Kanagawa, JP;
Atsushi Suzuki, Kanagawa, JP;
Assignee:
SONY CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N 5/3745 (2011.01); H03K 5/135 (2006.01); H03K 23/00 (2006.01); H03M 1/12 (2006.01); H03L 7/08 (2006.01); H04N 5/378 (2011.01); H03M 1/56 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H04N 5/37455 (2013.01); H03K 23/005 (2013.01); H03L 7/08 (2013.01); H03M 1/12 (2013.01); H03M 1/123 (2013.01); H04N 5/378 (2013.01); H03K 5/135 (2013.01); H03K 2005/00052 (2013.01); H03M 1/56 (2013.01);
Abstract
An A/D conversion device includes a phase-difference clock generation unit configured to use a plurality of phase interpolators to generate multi-phase clock signals, of which phases are shifted with respect to an input clock signal, from the input clock signal and a signal obtained by delaying the input clock signal; and an A/D conversion unit configured to perform A/D conversion on an input analog signal using the multi-phase clock signals generated by the phase-difference clock generation unit.