The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2020

Filed:

Jun. 27, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Robert Floyd Payne, Lucas, TX (US);

Olga Pavlovna Pope, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/081 (2006.01); H03F 3/68 (2006.01); H03D 7/12 (2006.01); H03F 3/45 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0818 (2013.01); H03D 7/125 (2013.01); H03F 3/45183 (2013.01); H03F 3/68 (2013.01); H03F 2203/45026 (2013.01); H03F 2203/45374 (2013.01);
Abstract

A multi-phase clock circuit includes a first delay circuit, a second delay circuit, a third delay circuit, a first clock mixer circuit, and a second clock mixer circuit. The first, second, and third delay circuits are coupled in series. The first clock mixer circuit includes a first input and a second input. The first input is coupled to an output of the first delay circuit. The second input is coupled to an output of the second delay circuit. The second clock mixer circuit also includes a first input and a second input. The first input of the second clock mixer circuit is coupled to an output of the second delay circuit. The second input of the second clock mixer circuit is coupled to an output of the third delay circuit.


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