The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2020

Filed:

Nov. 14, 2018
Applicant:

Omnivision Technologies, Inc., Santa Clara, CA (US);

Inventors:

Satoshi Sakurai, Cupertino, CA (US);

Hiroaki Ebihara, Santa Clara, CA (US);

Assignee:

OmniVision Technologies, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 23/00 (2006.01); H03M 1/12 (2006.01); H04N 5/357 (2011.01); H04N 5/378 (2011.01); H03M 1/56 (2006.01);
U.S. Cl.
CPC ...
H03K 23/005 (2013.01); H03M 1/1245 (2013.01); H03M 1/56 (2013.01); H04N 5/3575 (2013.01); H04N 5/378 (2013.01);
Abstract

An N bit counter includes a lower counter having a first output having M bits that operates a first counting frequency. An upper counter having a second output having N−M+L bits operates a second counting frequency. The second counting frequency is equal to the first counting frequency divided by 2. An error correction controller is coupled to receive the first and second outputs and perform operations that include comparing the L least significant bits (LSBs) of the second output and at least one most significant bit (MSB) of the first output, and correcting the N−M MSBs of the second output in response to the comparison. The lower bits of the N bit counter are the M bits of the first output, and the upper bits of the N bit counter are the corrected N−M MSBs of the second output.


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