The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2020

Filed:

Jun. 27, 2019
Applicant:

Nichia Corporation, Anan-shi, Tokushima, JP;

Inventors:

Shinichi Daikoku, Tokushima, JP;

Hirofumi Nishiyama, Tokushima, JP;

Assignee:

NICHIA CORPORATION, Anan-Shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/62 (2010.01); H01L 27/15 (2006.01); H01L 33/46 (2010.01); H01L 33/60 (2010.01); H01L 33/30 (2010.01); H01L 33/50 (2010.01); H01L 33/00 (2010.01); H01L 33/32 (2010.01);
U.S. Cl.
CPC ...
H01L 27/156 (2013.01); H01L 33/46 (2013.01); H01L 33/60 (2013.01); H01L 33/62 (2013.01); H01L 33/0079 (2013.01); H01L 33/30 (2013.01); H01L 33/32 (2013.01); H01L 33/502 (2013.01); H01L 2933/0016 (2013.01); H01L 2933/0025 (2013.01); H01L 2933/0058 (2013.01); H01L 2933/0066 (2013.01);
Abstract

A method of manufacturing a light emitting device includes: providing a wafer that comprises: a supporting substrate, and a plurality of light emitting structures arranged in a two-dimensional array on a first principal surface of the supporting substrate along a first direction and a second direction, each of the plurality of light emitting structures comprising a first semiconductor layer, which includes a first region and a second region, and a second semiconductor layer, which covers the second region of the first semiconductor layer, wherein the plurality of light emitting structures includes a first light emitting structure and a second light emitting structure; forming a recess in the first principal surface of the supporting substrate between the first light emitting structure and the second light emitting structure; forming a resin layer in the recess; and removing the supporting substrate so as to expose the first semiconductor layer.


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