The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2020

Filed:

Jul. 10, 2018
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Edward J. Nowak, Shelburne, VT (US);

Richard F. Taylor, Campbell, CA (US);

Tamilmani Ethirajan, Guilderland, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/10 (2006.01); H03K 17/687 (2006.01); H01L 21/762 (2006.01); H03K 17/693 (2006.01); H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1207 (2013.01); H01L 21/76224 (2013.01); H01L 21/84 (2013.01); H01L 29/1087 (2013.01); H03K 17/6871 (2013.01); H03K 17/693 (2013.01);
Abstract

The present disclosure relates to semiconductor structures and, more particularly, to virtual drains for decreased harmonic generation in fully depleted SOI (FDSOI) RF switches and methods of manufacture. The structure includes one or more active devices on a semiconductor on insulator material which is on top of a substrate; and a virtual drain region composed of a well region within the substrate and spaced apart from an active region of the one or more devices, the virtual drain region configured to be biased to collect electrons which would accumulate in the substrate.


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