The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2020

Filed:

Apr. 18, 2018
Applicant:

Solid State Storage Technology Corporation, Taipei, TW;

Inventors:

Shih-Jia Zeng, Taipei, TW;

Jen-Chien Fu, Taipei, TW;

Tsu-Han Lu, Taipei, TW;

Kuan-Chun Chen, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 29/44 (2006.01); G06F 11/07 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 29/4401 (2013.01); G06F 11/0727 (2013.01); G06F 11/0754 (2013.01); G11C 11/5642 (2013.01); G11C 16/0408 (2013.01); G11C 16/26 (2013.01);
Abstract

A failure mode detection method is provided. A first default read voltage is changed to a first read retry voltage by a first increment, and a second default read voltage is changed to a second read retry voltage by a second increment. A memory cell array of a solid state storage device is successfully read according to the first and second read retry voltages. If an absolute value of the first increment minus an absolute value of the second increment is larger than a predetermined voltage value, the memory cell array is in a data retention failure mode. If the absolute value of the first increment minus the absolute value of the second increment is smaller than the predetermined voltage value, the memory cell array is in a low temperature write high temperature read failure mode.


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