The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2020
Filed:
Nov. 14, 2016
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventors:
Yuichiro Ishii, Tokyo, JP;
Shinji Tanaka, Tokyo, JP;
Assignee:
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/419 (2006.01); G11C 5/06 (2006.01); G11C 8/14 (2006.01); G11C 11/418 (2006.01); H01L 27/11 (2006.01); G11C 5/14 (2006.01); G11C 7/12 (2006.01); G11C 8/08 (2006.01); G11C 7/02 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 5/063 (2013.01); G11C 5/145 (2013.01); G11C 7/12 (2013.01); G11C 8/08 (2013.01); G11C 8/14 (2013.01); G11C 11/418 (2013.01); H01L 27/1104 (2013.01); H01L 27/1116 (2013.01); G11C 7/02 (2013.01);
Abstract
A semiconductor storage device includes a plurality of memory cells arranged in a matrix, a word line provided corresponding to a memory cell row, a dummy word line formed in a metal interconnection layer adjacent to a metal interconnection layer in which the word line is formed, a word driver circuit configured to drive the word line, and a dummy word driver circuit configured to increase voltage on the word line based on interline capacitance between the word line and the dummy word line.