The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2020

Filed:

Oct. 12, 2016
Applicant:

Sharp Kabushiki Kaisha, Sakai, Osaka, JP;

Inventors:

Toshitsugu Sueki, Sakai, JP;

Yasuaki Iwase, Sakai, JP;

Takuya Watanabe, Sakai, JP;

Assignee:

SHARP KABUSHIKI KAISHA, Sakai, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 19/00 (2006.01); G09G 3/36 (2006.01); G11C 19/28 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3674 (2013.01); G09G 3/3677 (2013.01); G11C 19/28 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01);
Abstract

A shift register is implemented that can increase the reliability of long-term operation regarding the driving of gate bus lines over a conventional configuration. The shift register is allowed to operate by clock signals of eight or more phases with an on-duty of less than ½. A stabilization node control portion brings a stabilization node (NB) to an on level for a period less than 50 percent of a normal operation period, based on two or more clock signals among the clock signals of eight or more phases, the stabilization node (NB) being connected to a gate terminal of a thin film transistor that contributes to the drawing of a potential of an output control node (NA) to a VSS potential.


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