The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2020

Filed:

Sep. 30, 2019
Applicant:

Alibaba Group Holding Limited, George Town, KY;

Inventors:

Changzheng Wei, Hangzhou, CN;

Guozhen Pan, Hangzhou, CN;

Ying Yan, Hangzhou, CN;

Huabing Du, Hangzhou, CN;

Boran Zhao, Hangzhou, CN;

Xuyang Song, Hangzhou, CN;

Yichen Tu, Hangzhou, CN;

Ni Zhou, Hangzhou, CN;

Jianguo Xu, Hangzhou, CN;

Assignee:

Alibaba Group Holding Limited, George Town, Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/06 (2006.01); G06F 21/76 (2013.01); H04L 9/08 (2006.01); G06F 9/455 (2018.01); H04L 9/06 (2006.01);
U.S. Cl.
CPC ...
G06F 21/76 (2013.01); G06F 9/455 (2013.01); H04L 9/0819 (2013.01); H04L 9/0866 (2013.01); H04L 9/0869 (2013.01); H04L 9/0897 (2013.01); H04L 9/0643 (2013.01); H04L 2209/38 (2013.01);
Abstract

Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage media, for configuring a field programmable gate array (FPGA) based trusted execution environment (TEE) for use in a blockchain network. One of the methods includes storing a device identifier (ID), a first random number, and a first encryption key in a field programmable gate array (FPGA) device; sending an encrypted bitstream to the FPGA device, wherein the encrypted bitstream can be decrypted by the first key into a decrypted bitstream comprising a second random number; receiving an encrypted message from the FPGA device; decrypting the encrypted message from the FPGA device using a third key to produce a decrypted message; in response to decrypting the encrypted message: determining a third random number in the decrypted message; encrypting keys using the third random number; and sending the keys to the FPGA device.


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