The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2020

Filed:

Dec. 20, 2017
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Ramakrishna G. Poolla, Hyderabad, IN;

Krishna C. Patakamuri, Hyderabad, IN;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/00 (2013.01); G06F 21/57 (2013.01); G06F 21/74 (2013.01); G06F 21/60 (2013.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 21/577 (2013.01); G06F 3/0619 (2013.01); G06F 21/602 (2013.01); G06F 21/74 (2013.01); G06F 2221/2107 (2013.01);
Abstract

Method and system generally relating to integrated circuits are disclosed. In such a method, a secure lockdown mode for the integrated circuit is initiated. System states of a system internal to the integrated circuit are obtained after initiation of the secure lockdown mode. This obtaining of the system states includes: reading out of the system states from storage devices internal to the integrated circuit; and loading the system states into temporary storage of the integrated circuit. The system states are output via a port of the integrated circuit before closing the port responsive to the secure lockdown mode.


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