The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2020
Filed:
Feb. 28, 2017
Oregon State University, Corvallis, OR (US);
Lizhong Chen, Portland, OR (US);
Fawaz M. Alazemi, Corvallis, OR (US);
Bella Bose, Corvallis, OR (US);
Oregon State University, Corvallis, OR (US);
Abstract
The disclosed technology concerns methods, apparatus, and systems for designing and generating networks-on-chip ('NoCs'), as well as to hardware architectures for implementing such NoCs. The disclosed NoCs can be used, for instance, to interconnect cores of a chip multiprocessor (aka a 'multi-core processor'). In one example implementation, a wire-based routerless NoC design is disclosed that uses deterministically specified wire loops to connect the cores of the chip multiprocessor. The disclosed technology also comprises network interface architectures for use in an NoC. For example, a core can be equipped with a low-area-cost interface that is deadlock-free, uses buffering sharing, and provides low latency.