The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2020
Filed:
Apr. 20, 2018
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventors:
Limor Plotkin, Even Yehuda, IL;
Shiran Raz, Ganey Tikva, IL;
Yaniv Maroz, Kiryat Uno, IL;
Ofer Geva, Ramat HaSaron, IL;
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5045 (2013.01); G06F 17/505 (2013.01); G06F 2217/02 (2013.01); G06F 2217/04 (2013.01);
Abstract
Zero wire load based assertions are generated. A zero wire load report is generated for a set of logic in a hardware description language corresponding to a circuit design. A set of assertions is identified for the circuit design by parsing the zero wire load report based in part on real data values corresponding to best case delays for one or more input pins and one or more output pins in a plurality of macros of the circuit design. A circuit may be fabricated based on the set of assertions.