The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2020

Filed:

Feb. 13, 2018
Applicant:

Tsinghua University, Beijing, CN;

Inventors:

Leibo Liu, Beijing, CN;

Ao Luo, Beijing, CN;

Shaojun Wei, Beijing, CN;

Assignee:

TSINGHUA UNIVERSITY, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/34 (2006.01); G06F 21/71 (2013.01); G06F 21/56 (2013.01);
U.S. Cl.
CPC ...
G06F 11/3485 (2013.01); G06F 11/348 (2013.01); G06F 11/349 (2013.01); G06F 11/3476 (2013.01); G06F 21/566 (2013.01); G06F 21/71 (2013.01);
Abstract

The disclosure provides an input and output recording device and method, CPU and data read and write operation method thereof. The input and output recording device is provided between a central processor CPU and a peripheral, and is configured to record data read and write operations between the CPU and the peripheral, wherein the data read and write operations comprise a data read and write operation initiated by the peripheral and a data read and write operation initiated by the CPU; the input and output recording device is further configured to request the CPU to process the data read and write operation initiated by the peripheral, and upon receiving an instruction sent by the CPU, send a data packet of the data read and write operation initiated by the peripheral to the CPU. The disclosure can accurately record the data read and write operation between the CPU and the peripheral, so as to eliminate the influence of uncertainty caused by the asynchronous data read and write operations initiated by the peripherals, and provide a basis for the input and output security checking of the CPU.


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