The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2020

Filed:

Feb. 21, 2018
Applicant:

Everspin Technologies, Inc., Chandler, AZ (US);

Inventors:

Kurt Baty, Austin, TX (US);

Terry Van Hulett, Austin, TX (US);

Assignee:

Everspin Technologies, Inc., Chandler, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/20 (2006.01); G06F 11/10 (2006.01); G11C 29/00 (2006.01); G11C 29/44 (2006.01); G06F 11/07 (2006.01); G06F 11/30 (2006.01);
U.S. Cl.
CPC ...
G06F 11/2094 (2013.01); G06F 11/076 (2013.01); G06F 11/0727 (2013.01); G06F 11/106 (2013.01); G06F 11/3037 (2013.01); G11C 29/00 (2013.01); G11C 29/4401 (2013.01); G11C 29/76 (2013.01); G06F 2201/805 (2013.01); G06F 2201/82 (2013.01); G06F 2201/85 (2013.01);
Abstract

The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes scanning a first memory region for bit errors; in response to detecting one or more bit errors in the first memory region, incrementing a counter associated with the first memory region based on the number of bit errors detected; comparing a total number of bit errors against a threshold, wherein the total number of bit errors is identified from the first counter; and, if the total number of bit errors exceeds the threshold, restricting access to the first memory region by mapping an address corresponding to the first memory region to a second memory region.


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