The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2020

Filed:

Jun. 08, 2017
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Jung-Hyun Kwon, Seoul, KR;

Sung-Eun Lee, Gyeonggi-do, KR;

Sang-Gu Jo, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0604 (2013.01); G06F 3/064 (2013.01); G06F 3/0616 (2013.01); G06F 3/0653 (2013.01); G06F 3/0679 (2013.01); G06F 3/0685 (2013.01); G06F 12/0246 (2013.01); G06F 12/0638 (2013.01); G06F 2212/205 (2013.01); G06F 2212/7211 (2013.01);
Abstract

A memory system comprises a memory device including a plurality of memory blocks, a write operation check unit configured to count the number of write operations performed on the respective memory blocks, a write count distribution management module configured to manage a distribution of the memory blocks based on the counted number of the write operations, and a wear leveling module configured to detect hot and cold memory blocks from the plurality of memory blocks based on the counted number of the write operation and the distribution, wherein the wear leveling module manages a history of the hot memory block and swaps the hot memory block with the cold memory block according to the managed history.


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