The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2020

Filed:

Mar. 03, 2017
Applicant:

Sharp Kabushiki Kaisha, Sakai, Osaka, JP;

Inventor:

Hiroshi Matsukizono, Sakai, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1362 (2006.01); H01L 29/66 (2006.01); G02F 1/1368 (2006.01); G09F 9/00 (2006.01); G09F 9/30 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); G02F 1/1343 (2006.01);
U.S. Cl.
CPC ...
G02F 1/136209 (2013.01); G02F 1/1368 (2013.01); G02F 1/136286 (2013.01); G09F 9/00 (2013.01); G09F 9/30 (2013.01); H01L 27/1225 (2013.01); H01L 29/42384 (2013.01); H01L 29/4908 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78633 (2013.01); H01L 29/78696 (2013.01); G02F 1/134363 (2013.01); G02F 2001/13685 (2013.01); G02F 2201/40 (2013.01);
Abstract

A semiconductor apparatus () is provided with: a substrate (); and a thin-film transistor (). The thin-film transistor has: an oxide semiconductor layer () that includes a channel region () and first and second contact regions (); a gate insulating layer () that is provided so as to cover the oxide semiconductor layer; a gate electrode () that is provided on the gate insulating layer and that overlaps the channel region via the gate insulating layer; a source electrode () that is electrically connected to the first contact region; and a drain electrode () that is electrically connected to the second contact region. This semiconductor apparatus is further provided with a light-shielding layer () arranged between the oxide semiconductor layer and the substrate, and the channel region is aligned to the part of the light-shielding layer overlapping the oxide semiconductor layer.


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