The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2020

Filed:

Dec. 28, 2018
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Aliaksandr Subotski, Villach, AT;

Giuseppe Bernacchia, Villach, AT;

Danny Clavette, Greene, RI (US);

Benjamim Tang, Rancho Palos Verdes, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/40 (2020.01); H02M 3/156 (2006.01); H02M 1/08 (2006.01); H02H 7/12 (2006.01); G01N 25/72 (2006.01); H02M 1/32 (2007.01); H02M 1/00 (2006.01); H02H 3/04 (2006.01); H02M 3/158 (2006.01);
U.S. Cl.
CPC ...
G01R 31/40 (2013.01); G01N 25/72 (2013.01); H02H 7/12 (2013.01); H02H 7/1213 (2013.01); H02M 1/08 (2013.01); H02M 1/32 (2013.01); H02M 3/156 (2013.01); H02H 3/04 (2013.01); H02M 3/1584 (2013.01); H02M 2001/0032 (2013.01); H02M 2001/325 (2013.01); H02M 2001/327 (2013.01);
Abstract

A voltage regulator controller includes a first pin for receiving aggregate temperature information from a plurality of power stages, a plurality of second pins each for receiving phase current information from one of the power stages, control circuitry for controlling the power stages, detection circuitry for detecting signal levels at the first and second pins, and fault analysis circuitry for identifying the type of reported fault and the power stage that reported the fault based on the detected signal levels at the first and second pins and state information accessible by the controller. Aggregate temperature information is reported at the first pin in a first nominal range, and phase current information is reported at each of the second pins in a second nominal range. Each reported fault type has a unique fault signature at the first and second pins, which is outside at least one of the nominal ranges.


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