The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2020
Filed:
Jun. 08, 2017
Applicant:
Nxp B.v., Eindhoven, NL;
Inventors:
Joppe Willem Bos, Wijgmaal, BE;
Jan Hoogerbrugge, Helmond, NL;
Marc Joye, Palo Alto, CA (US);
Wilhelmus Petrus Adrianus Johannus Michiels, Reusel, NL;
Assignee:
NXP B.V., Eindhoven, NL;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/00 (2013.01); H04L 9/06 (2006.01); H04L 9/30 (2006.01); G09C 1/00 (2006.01); G06F 21/60 (2013.01);
U.S. Cl.
CPC ...
H04L 9/0631 (2013.01); G06F 21/602 (2013.01); G06F 21/604 (2013.01); G09C 1/00 (2013.01); H04L 9/30 (2013.01); H04L 2209/12 (2013.01); H04L 2209/16 (2013.01);
Abstract
A method for producing a white-box implementation of a cryptographic function using garbled circuits, including: producing, by a first party, a logic circuit implementing the cryptographic function using a plurality of logic gates and a plurality of wires; garbling the produced logic circuit, by the first party, including garbling the plurality of logic gates and assigning two garbled values for each of the plurality of wires; and providing a second party the garbled logic circuit and a first garbled circuit input value.