The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2020

Filed:

Jul. 09, 2018
Applicant:

Avago Technologies International Sales Pte. Limited, Singapore, SG;

Inventors:

Velu Pillai, Austin, TX (US);

Vivek Telang, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); G06F 13/40 (2006.01); G06F 13/14 (2006.01); H04L 12/40 (2006.01); H04L 25/00 (2006.01); H04L 29/06 (2006.01); G06F 13/42 (2006.01); H04L 1/00 (2006.01); H04L 25/49 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0091 (2013.01); G06F 13/14 (2013.01); G06F 13/4022 (2013.01); G06F 13/4072 (2013.01); G06F 13/4286 (2013.01); H04L 1/0042 (2013.01); H04L 1/0047 (2013.01); H04L 7/0087 (2013.01); H04L 12/40 (2013.01); H04L 25/00 (2013.01); H04L 69/08 (2013.01); H04L 25/4906 (2013.01); Y02D 10/14 (2018.01); Y02D 10/151 (2018.01);
Abstract

A system side interface of a PHY chip used in conjunction with a 100 GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an 'overclocked' NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.


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