The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2020
Filed:
May. 23, 2019
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Raymond Kong, San Jose, CA (US);
Hao Yu, Broomfield, CO (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/17756 (2020.01); H03K 19/17728 (2020.01); H03K 19/17736 (2020.01); H03K 19/1776 (2020.01); G06F 30/34 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/3312 (2020.01);
U.S. Cl.
CPC ...
H03K 19/17756 (2013.01); G06F 30/3312 (2020.01); G06F 30/34 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H03K 19/1774 (2013.01); H03K 19/1776 (2013.01); H03K 19/17728 (2013.01);
Abstract
A device includes a platform implemented in programmable circuitry of the device. The platform is configured to communicate with a host data processing system. The device includes a first partial reconfiguration region implemented in the programmable circuitry and coupled to the platform. The first partial reconfiguration region is reserved for implementing user-specified circuitry. The device includes timing insulation circuitry implemented in the programmable circuitry and configured to isolate timing of signals passing between the platform and the first partial reconfiguration region.