The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2020

Filed:

Feb. 05, 2019
Applicant:

Maxlinear, Inc., Carlsbad, CA (US);

Inventors:

Abhishek Jajoo, Carlsbad, CA (US);

Vamsi Paidi, Carlsbad, CA (US);

Assignee:

MAXLINEAR, INC., Carlsbad, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03F 3/45 (2006.01); H03F 3/195 (2006.01); H03F 1/52 (2006.01);
U.S. Cl.
CPC ...
H03F 3/45179 (2013.01); H03F 1/523 (2013.01); H03F 3/195 (2013.01); H03F 3/45188 (2013.01); H03F 2200/171 (2013.01); H03F 2200/222 (2013.01); H03F 2200/294 (2013.01); H03F 2200/336 (2013.01); H03F 2200/451 (2013.01); H03F 2203/45166 (2013.01); H03F 2203/45386 (2013.01); H03F 2203/45464 (2013.01);
Abstract

Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA includes first and second differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may include: a first inductor with a first terminal capacitively-coupled to a gate terminal of the first differential pair transistor and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first differential pair transistor, the fourth inductor may be coupled to a source terminal of the second differential pair transistor, and the third inductor may be capacitively-coupled to a gate terminal of the second differential pair transistor and also to ground. The second inductor may be embedded within the first inductor.


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