The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2020

Filed:

Sep. 09, 2016
Applicants:

University of Florida Research Foundation, Incorporated, Gainesville, FL (US);

Nanoholdings, Llc, Rowayton, CT (US);

Inventors:

Hyeonggeun Yu, Raleigh, NC (US);

Franky So, Cary, NC (US);

Do Young Kim, Jenks, OK (US);

Bhabendra K. Pradhan, Marietta, GA (US);

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 51/10 (2006.01); H01L 51/05 (2006.01); H01L 27/144 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 27/28 (2006.01); H01L 51/00 (2006.01); H01L 51/42 (2006.01); H01L 51/44 (2006.01); H01L 27/30 (2006.01);
U.S. Cl.
CPC ...
H01L 51/105 (2013.01); H01L 21/823487 (2013.01); H01L 27/1443 (2013.01); H01L 27/286 (2013.01); H01L 29/0847 (2013.01); H01L 29/41733 (2013.01); H01L 51/0021 (2013.01); H01L 51/057 (2013.01); H01L 51/0525 (2013.01); H01L 27/283 (2013.01); H01L 27/305 (2013.01); H01L 51/0023 (2013.01); H01L 51/0046 (2013.01); H01L 51/0558 (2013.01); H01L 51/426 (2013.01); H01L 51/441 (2013.01);
Abstract

A vertical field-effect transistor is provided, comprising a first electrode, a porous conductor layer formed from a layer of conductive material with a plurality of holes extending through the conductive material disposed therein, a dielectric layer between the first electrode and the porous conductor layer, a charge transport layer in contact with the porous conductor layer, and a second electrode electrically connected to the charge transport layer. A photoactive layer may be provided between the dielectric layer and the first electrode. A method of manufacturing a vertical field-effect transistor may also be provided, comprising forming a dielectric layer and depositing a conductor layer in contact with the dielectric layer, wherein one or more regions of the dielectric layer are masked during deposition such that the conductor layer includes a plurality of pores that extend through the conductor layer.


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