The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2020

Filed:

Oct. 03, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Hye Seung Yu, Gyeonggi-do, KR;

Won Joo Yun, Gyeonggi-do, KR;

Hyun Ui Lee, Gyeonggi-do, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/538 (2006.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); G11C 5/02 (2013.01); H01L 23/481 (2013.01); H01L 23/538 (2013.01); H01L 2224/13025 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01);
Abstract

A memory package includes a plurality of memory chips stacked on a package substrate. A logic chip is disposed between the plurality of memory chips and the package substrate. The logic chip is configured to control the plurality of memory chips through a plurality of vias passing through the plurality of memory chips. An intermediate chip is connected to the plurality of vias. The intermediate chip is disposed between the plurality of memory chips and the logic chip, and is configured to select at least a subset of the plurality of vias as a data transmission path between the logic chip and the plurality of memory chips, based on a data transmission rate of the logic chip.


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