The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2020

Filed:

Dec. 31, 2018
Applicant:

Juniper Networks, Inc., Sunnyvale, CA (US);

Inventors:

Erik Johan Norberg, Santa Barbara, CA (US);

Naser Dalvand, Mountain View, CA (US);

Gregory Alan Fish, Santa Barbara, CA (US);

Assignee:

Juniper Networks, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/42 (2006.01); H01L 29/868 (2006.01); H01L 27/12 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01); H01L 23/36 (2006.01);
U.S. Cl.
CPC ...
H01L 23/42 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/36 (2013.01); H01L 27/1203 (2013.01); H01L 29/6609 (2013.01); H01L 29/868 (2013.01);
Abstract

The thermal impedance of p-i-n diodes integrated on semiconductor-on-insulator substrates can be reduced with thermally conducting vias that shunt heat across thermal barriers such as, e.g., the thick top oxide cladding often encapsulating the p-i-n diode. In various embodiments, one or more thermally conducting vias extend from a top surface of the intrinsic diode layer to a metal structure connected to the doped top layer of the diode, and/or from that metal structure down to at least the semiconductor device layer of the substrate.


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