The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2020

Filed:

Dec. 29, 2017
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Pushpa Mahalingam, Richardson, TX (US);

Umamaheswari Aghoram, Richardson, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 21/321 (2006.01); H01L 21/285 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28035 (2013.01); H01L 21/0245 (2013.01); H01L 21/0262 (2013.01); H01L 21/02488 (2013.01); H01L 21/02502 (2013.01); H01L 21/02532 (2013.01); H01L 21/28525 (2013.01); H01L 21/321 (2013.01); H01L 29/42372 (2013.01); H01L 29/4916 (2013.01); H01L 29/4925 (2013.01); H01L 29/6659 (2013.01); H01L 29/66568 (2013.01); H01L 21/02592 (2013.01); H01L 21/02667 (2013.01);
Abstract

A method of forming a semiconductor device includes forming source regions and drain regions in a semiconductor substrate, and a gate electrode over said semiconductor substrate and between said source and drain regions. The gate electrode is formed from a first semiconductor gate electrode layer deposited on said gate dielectric layer at a first substrate temperature. A second semiconductor gate electrode layer is deposited on the first semiconductor gate electrode layer at a second substrate temperature greater than said first temperature. The two gate electrode layers may be annealed to form a homogenous polycrystalline layer with improved grain size distribution, thereby improving transistor matching in a semiconductor device.


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