The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2020
Filed:
Jan. 07, 2019
Applicant:
Vanguard International Semiconductor Corporation, Hsinchu, TW;
Inventors:
Assignee:
VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION, Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02645 (2013.01); H01L 21/0242 (2013.01); H01L 21/0245 (2013.01); H01L 21/0254 (2013.01); H01L 21/02389 (2013.01); H01L 21/02502 (2013.01); H01L 21/02516 (2013.01); H01L 29/66462 (2013.01); H01L 29/7787 (2013.01); H01L 21/02488 (2013.01);
Abstract
A method for manufacturing a semiconductor device structure is provided. The method includes providing a base substrate and forming a buffer layer on the base substrate. The method also includes forming a patterned silicon layer on the buffer layer. The patterned silicon layer has an opening to expose a portion of the buffer layer. The method further includes epitaxially growing a patterned channel layer and a patterned barrier layer on a top surface of the patterned silicon layer sequentially. In addition, the method includes forming a gate electrode on the patterned barrier layer.