The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2020

Filed:

Mar. 16, 2018
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Yusuke Shimada, Yokkaichi Mie, JP;

Fumitaka Arai, Yokkaichi Mie, JP;

Tatsuya Kato, Yokkaichi Mie, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/26 (2006.01); H01L 27/1157 (2017.01); G11C 16/04 (2006.01); H01L 27/11582 (2017.01); H01L 27/11565 (2017.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 16/0483 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); H01L 27/11582 (2013.01);
Abstract

A semiconductor memory device includes a first NAND string and a second NAND string sharing a channel and being connected in parallel. When reading a value from a first memory cell transistor of the first NAND string, a first potential is applied to a gate of a second memory cell transistor of the first NAND string and a gate of at least one of fourth memory cell transistors opposing the second memory cell transistor, a second potential is applied to a gate of a third memory cell transistor of the second NAND string opposing the first memory cell transistor, and a gate potential of the first memory cell transistor is swept between the second potential and the first potential. The second potential is lower than the first potential.


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