The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2020
Filed:
Sep. 21, 2017
Applicant:
Nokia Solutions and Networks Oy, Espoo, FI;
Inventors:
Paul J. Brown, Wakefield, CA;
Alex L. Chan, Ottawa, CA;
Assignee:
Nokia Solutions and Networks Oy, Espoo, FI;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/39 (2020.01); G06F 30/394 (2020.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 30/39 (2020.01); G06F 30/394 (2020.01);
Abstract
A printed circuit board (PCB) having a layout aligned with a Ball Grid Array (BGA) package, the PCB including a plurality of victim vias arranged in the PCB, at least one aggressor via arranged in the PCB having a transition with at least one victim via, wherein the transition is a space in the PCB between a victim via and an aggressor via along a row direction or a column direction, and the victim via is not positioned next to more than one transition.
Brown, Paul. (2020). Spatial location of vias in a printed circuit board (U.S. Patent No. 10650181). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10650181
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile