The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2020

Filed:

Apr. 10, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Rina Kipnis, Kiriat Motzkin, IL;

Vadim Liberchuk, Karmiel, IL;

Alex Raphayevich, Kiryat Ekron, IL;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5077 (2013.01); G06F 17/5031 (2013.01); G06F 17/5081 (2013.01); G06F 2217/02 (2013.01); G06F 2217/06 (2013.01); G06F 2217/12 (2013.01); G06F 2217/84 (2013.01);
Abstract

Generating reports for critical path evaluation and tuning. A predetermined critical path in a circuit design is detected. The predetermined critical path includes a plurality of interconnects between at least two macros. At least one output or at least one input is detected for each of the at least two macros associated with the predetermined critical path. Additionally, a routing description and a buffer location corresponding to the predetermined critical path are detected and a reduced layout design is built. The reduced layout design includes the predetermined critical path and the at least two macros. Furthermore, a timing report is generated based on the reduced layout design, and a circuit based on the circuit design is manufactured in response to detecting the timing report based on the reduced layout design satisfies a predetermined condition.


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