The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2020

Filed:

Dec. 21, 2017
Applicant:

Apple Inc., Cupertino, CA (US);

Inventor:

Harsha Krishnamurthy, San Jose, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H03K 3/037 (2006.01); H03K 3/012 (2006.01); G06F 1/10 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01); G06F 17/5077 (2013.01); H03K 3/012 (2013.01); H03K 3/037 (2013.01); G06F 1/10 (2013.01); G06F 2217/62 (2013.01); G06F 2217/78 (2013.01);
Abstract

Systems, apparatuses, and methods for efficiently implementing clock gating circuitry. A multi-bit clock gating cell is placed on the die of an integrated circuit and replaces at least two single-bit clock gating cells that were to be placed on the die. Each single-bit clock gating cell receives a single clock enable signal and generates a single gated clock signal. Each multi-bit clock gating cell receives multiple clock enable signals and generates multiple gated clock signals based on a single common received clock signal. Conditions for determining whether two or more single-bit clock gating cells are replaced by a multi-bit clock gating cell include a distance between two single-bit clock gating cells, a load driven by any one of the two single-bit clock gating cells and an activity level of a common single clock received by at least two single-bit clock gating cells is above a respective threshold.


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