The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2020

Filed:

May. 26, 2017
Applicant:

Dell Products, Lp, Round Rock, TX (US);

Inventors:

Mukund P. Khatri, Austin, TX (US);

Vijay Bharat Nijhawan, Austin, TX (US);

Assignee:

Dell Products, L.P., Round Rock, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 13/40 (2006.01); G06F 15/80 (2006.01); G06F 13/42 (2006.01); G06F 9/4401 (2018.01);
U.S. Cl.
CPC ...
G06F 13/4068 (2013.01); G06F 9/4405 (2013.01); G06F 13/4282 (2013.01); G06F 15/80 (2013.01); G06F 2213/0026 (2013.01);
Abstract

An information handling system includes an I/O device, a first processor die coupled to the I/O device, a second processor die coupled to the first processor die, and to no I/O device, and boot process logic. The boot process logic determines that the first processor die is coupled to the I/O device and that the second processor die is coupled to no I/O device, determines that an operating environment of the information handling system is capable of utilizing a maximum of Z processor cores, where Z is an integer number that is greater than X and less than the sum of X+Y, and enables Z processor cores on the first and second processor dies by enabling the X processor cores on the first processor die, and enabling the remainder of cores, equal to Z−X, on the second processor die, based upon the determination that the second processor die is coupled to no I/O device.


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