The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2020

Filed:

Dec. 30, 2016
Applicant:

Xockets, Inc., San Jose, CA (US);

Inventors:

Parin Bhadrik Dalal, Milpitas, CA (US);

Stephen Paul Belair, Santa Cruz, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 29/12 (2006.01); G06F 13/16 (2006.01); G06F 13/362 (2006.01); H04L 12/875 (2013.01); H04L 12/863 (2013.01); H04L 12/861 (2013.01); H04L 12/851 (2013.01); G06F 9/38 (2018.01); G06F 15/16 (2006.01); G06F 15/173 (2006.01); H04L 29/08 (2006.01); G06F 13/40 (2006.01); G06F 13/28 (2006.01); H04L 12/931 (2013.01);
U.S. Cl.
CPC ...
G06F 13/1652 (2013.01); G06F 9/3877 (2013.01); G06F 13/16 (2013.01); G06F 13/285 (2013.01); G06F 13/362 (2013.01); G06F 13/4022 (2013.01); G06F 13/4068 (2013.01); G06F 15/161 (2013.01); G06F 15/17337 (2013.01); H04L 29/08135 (2013.01); H04L 29/08549 (2013.01); H04L 47/2441 (2013.01); H04L 47/56 (2013.01); H04L 47/624 (2013.01); H04L 47/6295 (2013.01); H04L 49/90 (2013.01); H04L 61/103 (2013.01); H04L 61/2592 (2013.01); H04L 67/10 (2013.01); H04L 67/1097 (2013.01); H04L 49/40 (2013.01); H04L 61/6086 (2013.01); Y02D 10/14 (2018.01); Y02D 10/151 (2018.01);
Abstract

A network overlay system can include a data transport module having a network interface and a translation module configured to generate offload processing addresses for the network packet data; a system bus; at least one host processor connected to the system bus; and at least one offload processor module coupled to the system bus and configured to receive network packet data associated. Offload processor modules include processing circuits associated with at least one of the offload processing addresses that are configured to encapsulate the network packet data for transport on a logical network or decapsulate the network packet data received from the logical network. The offload processing circuits encapsulate or decapsulate network packet data independent of any host processor.


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