The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2020

Filed:

Feb. 21, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ekaterina M. Ambroladze, Somers, NY (US);

Deanna P. D. Berger, Hyde Park, NY (US);

Michael A. Blake, Wappingers Falls, NY (US);

Pak-kin Mak, Poughkeepsie, NY (US);

Robert J. Sonnelitter, III, Mount Vernon, NY (US);

Guy G. Tracy, Austin, TX (US);

Chad G. Wilson, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 12/0891 (2016.01); G06F 12/0804 (2016.01); G06F 12/0864 (2016.01); G06F 12/0897 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0891 (2013.01); G06F 12/0804 (2013.01); G06F 12/0864 (2013.01); G06F 12/0897 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/60 (2013.01);
Abstract

In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to each cache of the computing system activating the command, cache logic ends the quiesce of the computing system. Subsequent to ending the quiesce of the computing system, Cache logic purges storage addresses from the cache, based on the command, to the higher level memory.


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