The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2020
Filed:
Dec. 01, 2016
Applicant:
Cisco Technology, Inc., San Jose, CA (US);
Inventor:
Donald E. Steiss, Richardson, TX (US);
Assignee:
Cisco Technology, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 9/50 (2006.01); G06F 12/14 (2006.01); G06F 12/1027 (2016.01);
U.S. Cl.
CPC ...
G06F 9/3865 (2013.01); G06F 9/3016 (2013.01); G06F 9/30054 (2013.01); G06F 9/30101 (2013.01); G06F 9/30123 (2013.01); G06F 9/30134 (2013.01); G06F 9/3851 (2013.01); G06F 9/3861 (2013.01); G06F 9/5016 (2013.01); G06F 12/1027 (2013.01); G06F 12/1441 (2013.01); G06F 2212/681 (2013.01);
Abstract
Embodiments are generally directed to a multithreaded processor for executing a plurality of threads, as well as an associated method and system. The multithreaded processor comprises a first control register configured to store a stack limit value, and instruction decode logic configured to, upon receiving a procedure entry instruction for a stack associated with a first thread, determine whether to throw a stack limit exception based on the stack limit value and a first predefined stack region size associated with the stack.