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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10649602 B1

PDFFull Text
Date of Patent:
May. 12, 2020

Filed:

Jan. 16, 2019

Touch device

Applicant:

Innolux Corporation, Miao-Li County, TW;

Inventor:

Cheng-Min Wu, Miao-Li County, TW;

Assignee:

Innolux Corporation, Miao-Li County, TW;

Attorney:

JCIPRNET

Primary Examiner:

Koosha Sharifi-Tafreshi

Int. Cl.
CPC ...
G06F 3/044 (2006.01); G06F 3/041 (2006.01); H01L 27/02 (2006.01); G02F 1/1362 (2006.01); G02F 1/1333 (2006.01); G02F 1/1345 (2006.01); H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
G06F 3/044 (2013.01); G02F 1/13338 (2013.01); G02F 1/13454 (2013.01); G02F 1/136204 (2013.01); G06F 3/0412 (2013.01); H01L 27/0292 (2013.01); H01L 27/124 (2013.01); H01L 29/78633 (2013.01); G02F 2201/121 (2013.01); G06F 2203/04103 (2013.01); G06F 2203/04107 (2013.01); H01L 27/1214 (2013.01); H01L 27/323 (2013.01); H01L 27/3262 (2013.01); H01L 27/3272 (2013.01);
Abstract

A touch device including an array substrate, at least one gate driving circuit, an opposite substrate and a shielding pattern is provided. The array substrate has a display region and a peripheral region connecting to the display region. The gate driving circuit is disposed on the array substrate and located in the peripheral region. The opposite substrate is disposed opposite to the array substrate. The shielding pattern is disposed between the array substrate and the opposite substrate. The shielding pattern projected on the array substrate is formed a first projection, the gate driving circuit projected on the array substrate is formed a second projection, the first projection at least partially overlaps with the second projection.

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