The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2020

Filed:

Sep. 04, 2018
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Chengdu Boe Optoelectronics Technology Co., Ltd., Chengdu, Sichuan, CN;

Inventors:

Dong Pang, Beijing, CN;

Xiaofei Yang, Beijing, CN;

Dongjie Qin, Beijing, CN;

Xu Liu, Beijing, CN;

Zhengdong Zhang, Beijing, CN;

Mingzhou Guo, Beijing, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G02F 1/1362 (2006.01); G02F 1/1333 (2006.01); G02F 1/1368 (2006.01);
U.S. Cl.
CPC ...
G02F 1/136227 (2013.01); G02F 1/133345 (2013.01); G02F 1/136286 (2013.01); H01L 27/124 (2013.01); H01L 27/1248 (2013.01); H01L 27/1259 (2013.01); H01L 27/1288 (2013.01); G02F 1/1368 (2013.01); G02F 2001/136236 (2013.01);
Abstract

An array substrate and a method for manufacturing the same, a display panel and a display device are provided. The array substrate includes a gate layer, a gate insulation layer, a source-drain layer, a first passivation layer and an ITO layer successively formed on a base substrate, a first through hole in the first passivation layer and a second through hole in the gate insulation layer, and a second passivation layer; and a part of the second passivation layer is arranged in the first and second through holes to cover a part of the ITO layer in the first through hole and the second through hole.


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