The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2020

Filed:

Apr. 22, 2019
Applicant:

Newport Fab, Llc, Newport Beach, CA (US);

Inventors:

Edward Preisler, San Clemente, CA (US);

Oleg Martynov, Oceanside, CA (US);

Farnood Rezaie, Irvine, CA (US);

Assignee:

Newport Fab, LLC, Newport Beach, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/12 (2006.01); G02B 6/136 (2006.01); H01L 25/16 (2006.01); G02B 6/42 (2006.01);
U.S. Cl.
CPC ...
G02B 6/12002 (2013.01); G02B 6/136 (2013.01); G02B 6/4228 (2013.01); H01L 25/167 (2013.01); G02B 2006/12061 (2013.01); G02B 2006/12121 (2013.01); G02B 2006/12123 (2013.01); G02B 2006/12173 (2013.01); G02B 2006/12176 (2013.01);
Abstract

There are disclosed herein various implementations of a silicon-on-insulator (SOI) die including a light emitting layer pedestal-aligned with a light receiving segment, as well as methods for fabricating such an SOI die. The SOT die includes a pedestal region of the SOI die having a pedestal including a thin top silicon segment, a buried oxide (BOX) segment, and a handle wafer segment. The SOI die also includes an integrated circuit (IC) region having a thin silicon waveguide that is aligned with the thin top silicon segment in the pedestal region. A light emitting layer is situated over the pedestal in the pedestal region, the light emitting layer being aligned with the light receiving segment to situated over the thin silicon waveguide in the IC region.


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