The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Aug. 21, 2017
Applicant:

Barefoot Networks, Inc., Palo Alto, CA (US);

Inventors:

Gregory C. Watson, Palo Alto, CA (US);

Julianne Zhu, Los Gatos, CA (US);

Ravindra Sunkad, Pleasanton, CA (US);

Steven Licking, San Jose, CA (US);

Sachin Bahadur, Santa Clara, CA (US);

Assignee:

Barefoot Networks, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/28 (2006.01); H04L 12/947 (2013.01); G06F 13/16 (2006.01); H04L 12/801 (2013.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
H04L 49/252 (2013.01); G06F 13/1673 (2013.01); G06F 13/287 (2013.01); H04L 47/33 (2013.01);
Abstract

Some embodiments of the invention provide a network forwarding element that includes a set of data plane circuits with several configurable packet processing stages for receiving and processing incoming packet traffic to the forwarding element. The forwarding element also includes a set of control plane circuits that include a set of direct memory access (DMA) buffers for configuring the configurable packet processing stages of the data plane. The control plane loads configuration data for reconfiguring the data plane packet processing stages into the set of DMA buffers while the data plane packet processing stages are processing the incoming packet traffic. The control plane pauses the incoming packet traffic to the data plane packet processing stages. The control plane loads the configuration data from the DMA buffers into the data plane packet processing stages. The control plane resumes the incoming packet traffic to the data plane packet processing stages.


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