The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Mar. 26, 2019
Applicant:

The Governing Council of the University of Toronto, Toronto, CA;

Inventors:

Alhassan Khedr, Toronto, CA;

Glenn Gulak, Toronto, CA;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 9/00 (2006.01); H04L 9/06 (2006.01); G09C 1/00 (2006.01); G06F 9/30 (2018.01); G06F 7/50 (2006.01);
U.S. Cl.
CPC ...
H04L 9/008 (2013.01); G09C 1/00 (2013.01); H04L 9/0618 (2013.01); G06F 7/50 (2013.01); G06F 9/3001 (2013.01); G06F 9/30029 (2013.01); G06F 2207/4802 (2013.01); H04L 2209/12 (2013.01);
Abstract

Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, a number theoretic transform (NTT) butterfly circuit is disclosed. The (NTT) butterfly circuit includes a high input word path cross-coupled with a low word path. The high input word path includes a first adder/subtractor, a first multiplier, and first selection circuitry coupled to the first adder/subtractor and the first multiplier. Respective bypass paths selectively bypass the first adder/subtractor and the first multiplier. The low input word path includes a second adder/subtractor, a second multiplier, and second selection circuitry coupled to the second adder/subtractor and the second multiplier. Respective bypass paths selectively bypass the second adder/subtractor and the second multiplier. The first and second selection circuitry is responsive to different mode control signals to reconfigure the low and high input word paths into different logic processing units.


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